m44miri 
I want compile new kernel but I can't run Ethernet (dm9000aep). How i can run ethernet?can you get me driver and manual for this?
Problem at DM9000aep
Juergen Beisert
The DM9000 driver is part of any mainline Linux kernel since ages.
m44miri
well,Why, after activated it ,i don't look eth0 or something like that at the Ubuntu ,in the /etc/network/interface ? if this option is enabled (dm9000), Chipset dm9000aep working? Can you please help me?
Juergen Beisert
Activating in the kernel means only the driver is present. And yes, the DM9000AEP is supported, as it is a DM9000A and the trailing EP only means Pb free. Does a "ifconfig -a" show the eth0?
m44miri
OK .i 'm ganna checking today withe this command.
m44miri
I checked ,Unfortunately not work, I see 2 device with ifconfig -a dummy0 and loopback
Juergen Beisert
You should see two entries in the sysfs: - /sys/bus/platform/devices/dm9000 - /sys/bus/platform/drivers/dm9000 The 'dm9000' entry in "devices" is present, when your platform file registers the DM9000 device. The 'dm9000' entry in "drivers" is present, when your kernel's driver for the DM9000 is enabled. If one of these entries are missing, it cannot work.
m44miri
Thanks.I checked : root@ubuntu:~# ls /sys/bus/platform/devices/ Fixed MDIO bus.0 s3c2440-i2c.0 s3c6400-uart.1 s3c-fb smsc911x platform-lcd.0 s3c2440-i2c.1 s3c6400-uart.2 s3c-hsotg s3c2410-ohci s3c6400-uart.0 s3c6400-uart.3 s3c-sdhci.0 But i enabled dm9000 at the compile time so why is not in the list?!!!
m44miri
sorry ,i forget. root@ubuntu:~# ls /sys/bus/platform/drivers dm9000 dnet ethoc s3c6400-uart s3c-fb s3c-i2c s3c-sdhci s3c-ts in the drivers is & in the device isn't!!
m44miri
How can i register the DM9000 device in the platform file?
m44miri
I registered dm9000 with this method : http://www.oselas.org/oselas/bsp/pengutronix/download/OSELAS.BSP-Pengutr... but after compile and running look this message: Starting kernel ... Uncompressing Linux... done, booting the kernel. Linux version 2.6.32 (2.6.32) (root@m44miri) (gcc version 4.2.1) #3 Mon Apr 9 23:36:49 IRDT 2012 CPU: ARMv6-compatible processor [410fb766] revision 6 (ARMv7), cr=00c5387f CPU: VIPT nonaliasing data cache, VIPT nonaliasing instruction cache Machine: SMDK6410 Memory policy: ECC disabled, Data cache writeback CPU S3C6410 (id 0x36410101) S3C24XX Clocks, (c) 2004 Simtec Electronics S3C64XX: PLL settings, A=532000000, M=532000000, E=24000000 S3C64XX: HCLK2=266000000, HCLK=133000000, PCLK=66500000 mout_apll: source is fout_apll (1), rate is 532000000 mout_epll: source is fout_epll (1), rate is 24000000 mout_mpll: source is mpll (1), rate is 532000000 mmc_bus: source is mout_epll (0), rate is 24000000 mmc_bus: source is mout_epll (0), rate is 24000000 mmc_bus: source is mout_epll (0), rate is 24000000 usb-bus-host: source is clk_48m (0), rate is 48000000 uclk1: source is dout_mpll (1), rate is 66500000 spi-bus: source is mout_epll (0), rate is 24000000 spi-bus: source is mout_epll (0), rate is 24000000 audio-bus: source is mout_epll (0), rate is 24000000 audio-bus: source is mout_epll (0), rate is 24000000 irda-bus: source is mout_epll (0), rate is 24000000 camera: source is hclk2 (0), rate is 266000000 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512 Kernel command line: console=ttySAC0,115200 rootfstype=ext3 root=/dev/mmcblk0 PID hash table entries: 512 (order: -1, 2048 bytes) Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) Memory: 128MB = 128MB total Memory: 124500KB available (3452K code, 408K data, 1268K init, 0K highmem) SLUB: Genslabs=11, HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 Hierarchical RCU implementation. NR_IRQS:246 VIC @f4000000: id 0x00041192, vendor 0x41 VIC @f4010000: id 0x00041192, vendor 0x41 Console: colour dummy device 80x30 console [ttySAC0] enabled Calibrating delay loop... 530.84 BogoMIPS (lpj=2654208) Mount-cache hash table entries: 512 CPU: Testing write buffer coherency: ok NET: Registered protocol family 16 S3C6410: Initialising architecture bio: create slab <bio-0> at 0 SCSI subsystem initialized usbcore: registered new interface driver usbfs usbcore: registered new interface driver hub usbcore: registered new device driver usb s3c-i2c s3c2440-i2c.0: slave address 0x10 s3c-i2c s3c2440-i2c.0: bus frequency set to 64 KHz s3c-i2c s3c2440-i2c.0: i2c-0: S3C I2C adapter s3c-i2c s3c2440-i2c.1: slave address 0x10 s3c-i2c s3c2440-i2c.1: bus frequency set to 64 KHz s3c-i2c s3c2440-i2c.1: i2c-1: S3C I2C adapter NET: Registered protocol family 2 IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 4096 (order: 3, 32768 bytes) TCP bind hash table entries: 4096 (order: 4, 81920 bytes) TCP: Hash tables configured (established 4096 bind 4096) TCP reno registered NET: Registered protocol family 1 NetWinder Floating Point Emulator V0.97 (extended precision) JFFS2 version 2.2. (NAND) آ© 2001-2006 Red Hat, Inc. ROMFS MTD (C) 2007 Red Hat, Inc. fuse init (API version 7.13) alg: No test for stdrng (krng) io scheduler noop registered io scheduler anticipatory registered io scheduler deadline registered io scheduler cfq registered (default) Console: switching to colour frame buffer device 100x60 s3c-fb s3c-fb: window 0: fb s3c6400-uart.0: s3c2410_serial0 at MMIO 0x7f005000 (irq = 16) is a S3C6400/10 s3c6400-uart.1: s3c2410_serial1 at MMIO 0x7f005400 (irq = 20) is a S3C6400/10 s3c6400-uart.2: s3c2410_serial2 at MMIO 0x7f005800 (irq = 24) is a S3C6400/10 s3c6400-uart.3: s3c2410_serial3 at MMIO 0x7f005c00 (irq = 28) is a S3C6400/10 brd: module loaded loop: module loaded at24 0-0050: 1024 byte 24c08 EEPROM (writable) at24 1-0057: 16384 byte 24c128 EEPROM (writable) st: Version 20081215, fixed bufsize 32768, s/g segs 256 SCSI Media Changer driver v0.25 dm9000 Ethernet Driver, V1.31 dm9000 dm9000.0: insufficient resources dm9000 dm9000.0: not found (-2). Unable to handle kernel NULL pointer dereference at virtual address 00000010 pgd = c0004000 [00000010] *pgd=00000000 Internal error: Oops: 5 [#1] last sysfs file: Modules linked in: CPU: 0 Not tainted (2.6.32 #3) PC is at release_resource+0x10/0x64 LR is at release_resource+0x10/0x64 pc : [<c016d9d0>] lr : [<c016d9d0>] psr: a0000013 sp : c7821ed8 ip : c7821ed0 fp : 00000000 r10: c04c2f48 r9 : 00000000 r8 : c04c3100 r7 : 00000000 r6 : c7bc3000 r5 : fffffffe r4 : 00000000 r3 : 00000000 r2 : ffffffff r1 : 00000000 r0 : c04c6314 Flags: NzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel Control: 00c5387d Table: 50004008 DAC: 00000017 Process swapper (pid: 1, stack limit = 0xc7820268) Stack: (0xc7821ed8 to 0xc7822000) 1ec0: c7bc3300 c030d8a0 1ee0: c7bc3300 c03b59e0 00000000 c001b07c 00000000 c0200a40 c7842120 00000000 1f00: 00000000 c04c2f50 c04c2f84 c04e0864 c04e0864 c04de678 00000000 c001b07c 1f20: 00000000 c02d2070 c04e0864 c02d1134 c04c2f84 c04c2f50 c04c2f84 c04e0864 1f40: c04e0864 c02d1244 00000000 c7821f58 c02d11e4 c02d04ec c7802d08 c7840c40 1f60: c04e0864 c001f8f8 c04e0864 00000000 c7bd0540 c02d0ab8 c045799c c04e0864 1f80: c001f8f8 c04e0864 c04eae2c 00000000 00000000 c02d1534 00000000 c001f8f8 1fa0: c001f9e8 c04eae2c 00000000 00000000 c001b07c c0145398 00000030 00000000 1fc0: 00000000 000000f6 c001f8f8 c001f9e8 00000000 00000000 00000000 00000000 1fe0: 00000000 c000889c 00000000 00000000 00000000 c0146df8 ffffffff ffffffff [<c016d9d0>] (release_resource+0x10/0x64) from [<c030d8a0>] (dm9000_release_board+0x20/0x3c) [<c030d8a0>] (dm9000_release_board+0x20/0x3c) from [<c03b59e0>] (dm9000_probe+0x61c/0x6cc) [<c03b59e0>] (dm9000_probe+0x61c/0x6cc) from [<c02d2070>] (platform_drv_probe+0x1c/0x24) [<c02d2070>] (platform_drv_probe+0x1c/0x24) from [<c02d1134>] (driver_probe_device+0xa4/0x154) [<c02d1134>] (driver_probe_device+0xa4/0x154) from [<c02d1244>] (__driver_attach+0x60/0x84) [<c02d1244>] (__driver_attach+0x60/0x84) from [<c02d04ec>] (bus_for_each_dev+0x4c/0x80) [<c02d04ec>] (bus_for_each_dev+0x4c/0x80) from [<c02d0ab8>] (bus_add_driver+0x9c/0x22c) [<c02d0ab8>] (bus_add_driver+0x9c/0x22c) from [<c02d1534>] (driver_register+0xac/0x13c) [<c02d1534>] (driver_register+0xac/0x13c) from [<c0145398>] (do_one_initcall+0x58/0x19c) [<c0145398>] (do_one_initcall+0x58/0x19c) from [<c000889c>] (kernel_init+0x9c/0x118) [<c000889c>] (kernel_init+0x9c/0x118) from [<c0146df8>] (kernel_thread_exit+0x0/0x8) Code: e92d4010 e1a04000 e59f0050 eb092a9d (e5943010) ---[ end trace e4f1a58bebc91780 ]--- Kernel panic - not syncing: Attempted to kill init! [<c014ba94>] (unwind_backtrace+0x0/0xe0) from [<c0167e04>] (panic+0x44/0x124) [<c0167e04>] (panic+0x44/0x124) from [<c016abe8>] (do_exit+0x5c/0x5d0) [<c016abe8>] (do_exit+0x5c/0x5d0) from [<c0149e5c>] (die+0x144/0x16c) [<c0149e5c>] (die+0x144/0x16c) from [<c014c9b8>] (__do_kernel_fault+0x68/0x80) [<c014c9b8>] can you tell me about because problem?
Juergen Beisert
Why not taking a look into the DM9000 driver where any why it outputs the error message you see in your log: > dm9000 Ethernet Driver, V1.31 > dm9000 dm9000.0: insufficient resources > dm9000 dm9000.0: not found (-2).
m44miri
Yes.I see and I know. I really do not know why this problem. before dm9000 register this problem did not exist.This is the file that I have set.please look: /* linux/arch/arm/mach-s3c6410/mach-smdk6410.c * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> * http://armlinux.simtec.co.uk/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * */ #include <linux/kernel.h> #include <linux/types.h> #include <linux/interrupt.h> #include <linux/list.h> #include <linux/timer.h> #include <linux/init.h> #include <linux/serial_core.h> #include <linux/platform_device.h> #include <linux/io.h> #include <linux/i2c.h> #include <linux/fb.h> #include <linux/gpio.h> #include <linux/delay.h> #include <linux/smsc911x.h> #include <linux/dm9000.h> #ifdef CONFIG_SMDK6410_WM1190_EV1 #include <linux/mfd/wm8350/core.h> #include <linux/mfd/wm8350/pmic.h> #endif #include <video/platform_lcd.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/irq.h> #include <mach/hardware.h> #include <mach/regs-fb.h> #include <mach/map.h> #include <asm/irq.h> #include <asm/mach-types.h> #include <plat/regs-serial.h> #include <plat/regs-modem.h> #include <plat/regs-gpio.h> #include <plat/regs-sys.h> #include <plat/iic.h> #include <plat/fb.h> #include <plat/gpio-cfg.h> #include <plat/s3c6410.h> #include <plat/clock.h> #include <plat/devs.h> #include <plat/cpu.h> #define S3C64XX_PA_DM9000 (0x18000000) #define S3C64XX_SZ_DM9000 SZ_1M #define S3C64XX_VA_DM9000 S3C_ADDR(0x03b00300) #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = { [0] = { .hwport = 0, .flags = 0, .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, }, [1] = { .hwport = 1, .flags = 0, .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, }, [2] = { .hwport = 2, .flags = 0, .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, }, [3] = { .hwport = 3, .flags = 0, .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, }, }; static struct map_desc smdk6410_iodesc[] = { // #ifdef CONFIG_DM9000 { .virtual = (u32)S3C64XX_VA_DM9000, .pfn = __phys_to_pfn(S3C64XX_PA_DM9000), .length = S3C64XX_SZ_DM9000, .type = MT_DEVICE, }, // #endif }; static void __init smdk6410_map_io(void) { u32 tmp; s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc)); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs)); /* set the LCD type */ tmp = __raw_readl(S3C64XX_SPCON); tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK; tmp |= S3C64XX_SPCON_LCD_SEL_RGB; __raw_writel(tmp, S3C64XX_SPCON); /* remove the lcd bypass */ tmp = __raw_readl(S3C64XX_MODEM_MIFPCON); tmp &= ~MIFPCON_LCD_BYPASS; __raw_writel(tmp, S3C64XX_MODEM_MIFPCON); }; /* framebuffer and LCD setup. */ /* GPF15 = LCD backlight control * GPF13 => Panel power * GPN5 = LCD nRESET signal * PWM_TOUT1 => backlight brightness */ static void smdk6410_lcd_power_set(struct plat_lcd_data *pd, unsigned int power) { if (power) { gpio_direction_output(S3C64XX_GPF(13), 1); gpio_direction_output(S3C64XX_GPF(15), 1); /* fire nRESET on power up */ gpio_direction_output(S3C64XX_GPN(5), 0); msleep(10); gpio_direction_output(S3C64XX_GPN(5), 1); msleep(1); } else { gpio_direction_output(S3C64XX_GPF(15), 0); gpio_direction_output(S3C64XX_GPF(13), 0); } } static struct plat_lcd_data smdk6410_lcd_power_data = { .set_power = smdk6410_lcd_power_set, }; static struct platform_device smdk6410_lcd_powerdev = { .name = "platform-lcd", .dev.parent = &s3c_device_fb.dev, .dev.platform_data = &smdk6410_lcd_power_data, }; static struct s3c_fb_pd_win smdk6410_fb_win0 = { /* this is to ensure we use win0 */ .win_mode = { .pixclock = 41094, .left_margin = 8, .right_margin = 13, .upper_margin = 7, .lower_margin = 5, .hsync_len = 3, .vsync_len = 1, .xres = 800, .yres = 480, }, .max_bpp = 32, .default_bpp = 16, }; /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */ static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = { .setup_gpio = s3c64xx_fb_gpio_setup_24bpp, .win[0] = &smdk6410_fb_win0, .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, }; static struct resource smdk6410_smsc911x_resources[] = { [0] = { .start = 0x18000000, .end = 0x18000000 + SZ_64K - 1, .flags = IORESOURCE_MEM, }, [1] = { .start = S3C_EINT(10), .end = S3C_EINT(10), .flags = IORESOURCE_IRQ | IRQ_TYPE_LEVEL_LOW, }, }; static struct smsc911x_platform_config smdk6410_smsc911x_pdata = { .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY, .phy_interface = PHY_INTERFACE_MODE_MII, }; static struct platform_device smdk6410_smsc911x = { .name = "smsc911x", .id = -1, .num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources), .resource = &smdk6410_smsc911x_resources[0], .dev = { .platform_data = &smdk6410_smsc911x_pdata, }, }; /*static struct map_desc smdk6410_iodesc[] = { #ifdef CONFIG_DM9000 { .virtual = (u32)S3C64XX_VA_DM9000, .pfn = __phys_to_pfn(S3C64XX_PA_DM9000), .length = S3C64XX_SZ_DM9000, .type = MT_DEVICE, }, #endif }; */ #ifdef CONFIG_SMDK6410_WM1190_EV1 /* S3C64xx internal logic & PLL */ static struct regulator_init_data wm8350_dcdc1_data = { .constraints = { .name = "PVDD_INT/PVDD_PLL", .min_uV = 1200000, .max_uV = 1200000, .always_on = 1, .apply_uV = 1, }, }; /* Memory */ static struct regulator_init_data wm8350_dcdc3_data = { .constraints = { .name = "PVDD_MEM", .min_uV = 1800000, .max_uV = 1800000, .always_on = 1, .state_mem = { .uV = 1800000, .mode = REGULATOR_MODE_NORMAL, .enabled = 1, }, .initial_state = PM_SUSPEND_MEM, }, }; /* USB, EXT, PCM, ADC/DAC, USB, MMC */ static struct regulator_init_data wm8350_dcdc4_data = { .constraints = { .name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV", .min_uV = 3000000, .max_uV = 3000000, .always_on = 1, }, }; /* ARM core */ static struct regulator_consumer_supply dcdc6_consumers[] = { { .supply = "vddarm", } }; static struct regulator_init_data wm8350_dcdc6_data = { .constraints = { .name = "PVDD_ARM", .min_uV = 1000000, .max_uV = 1300000, .always_on = 1, .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, }, .num_consumer_supplies = ARRAY_SIZE(dcdc6_consumers), .consumer_supplies = dcdc6_consumers, }; /* Alive */ static struct regulator_init_data wm8350_ldo1_data = { .constraints = { .name = "PVDD_ALIVE", .min_uV = 1200000, .max_uV = 1200000, .always_on = 1, .apply_uV = 1, }, }; /* OTG */ static struct regulator_init_data wm8350_ldo2_data = { .constraints = { .name = "PVDD_OTG", .min_uV = 3300000, .max_uV = 3300000, .always_on = 1, }, }; /* LCD */ static struct regulator_init_data wm8350_ldo3_data = { .constraints = { .name = "PVDD_LCD", .min_uV = 3000000, .max_uV = 3000000, .always_on = 1, }, }; /* OTGi/1190-EV1 HPVDD & AVDD */ static struct regulator_init_data wm8350_ldo4_data = { .constraints = { .name = "PVDD_OTGI/HPVDD/AVDD", .min_uV = 1200000, .max_uV = 1200000, .apply_uV = 1, .always_on = 1, }, }; static struct { int regulator; struct regulator_init_data *initdata; } wm1190_regulators[] = { { WM8350_DCDC_1, &wm8350_dcdc1_data }, { WM8350_DCDC_3, &wm8350_dcdc3_data }, { WM8350_DCDC_4, &wm8350_dcdc4_data }, { WM8350_DCDC_6, &wm8350_dcdc6_data }, { WM8350_LDO_1, &wm8350_ldo1_data }, { WM8350_LDO_2, &wm8350_ldo2_data }, { WM8350_LDO_3, &wm8350_ldo3_data }, { WM8350_LDO_4, &wm8350_ldo4_data }, }; static int __init smdk6410_wm8350_init(struct wm8350 *wm8350) { int i; /* Configure the IRQ line */ s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP); /* Instantiate the regulators */ for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++) wm8350_register_regulator(wm8350, wm1190_regulators[i].regulator, wm1190_regulators[i].initdata); return 0; } static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = { .init = smdk6410_wm8350_init, .irq_high = 1, }; #endif static s...stripped-down
m44miri
and ...
static struct i2c_board_info i2c_devs0[] __initdata = {
{ I2C_BOARD_INFO("24c08", 0x50), },
{ I2C_BOARD_INFO("wm8580", 0x1b), },
#ifdef CONFIG_SMDK6410_WM1190_EV1
{ I2C_BOARD_INFO("wm8350", 0x1a),
.platform_data = &smdk6410_wm8350_pdata,
.irq = S3C_EINT(12),
},
#endif
};
static struct i2c_board_info i2c_devs1[] __initdata = {
{ I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */
};
/* Ethernet */
#define DM9000_ETH_IRQ_EINT0 IRQ_EINT(7)
static struct resource dm9000_resources[] = {
[0] = {
.start = S3C64XX_PA_DM9000,
//.end = S3C64XX_PA_DM9000 + 3,
.end = S3C64XX_VA_DM9000 + S3C64XX_SZ_DM9000 - 1,
.flags = IORESOURCE_MEM,
},
/*[1] = {
.start = S3C64XX_PA_DM9000 + 4,
.end = S3C64XX_PA_DM9000 + S3C64XX_SZ_DM9000 - 1,
.flags = IORESOURCE_MEM,
},*/
[1] = {
.start = IRQ_EINT(7),
.end = IRQ_EINT(7),
//.flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
.flags = IORESOURCE_IRQ,
},
};
static struct dm9000_plat_data dm9000_setup = {
.flags = DM9000_PLATF_16BITONLY,
//.dev_addr = { 0x08, 0x90, 0x00, 0xa0, 0x90, 0x90 },
};
struct platform_device s3c_device_dm9000 = {
.name = "dm9000",
.id = 0,
.num_resources = ARRAY_SIZE(dm9000_resources),
.resource = dm9000_resources,
.dev = {
.platform_data = &dm9000_setup,
}
};
/*static int __init dm9000_set_mac(char *str) {
unsigned char addr[6];
unsigned int val;
int idx = 0;
char *p = str, *end;
while (*p && idx < 6) {
val = simple_strtoul(p, &end, 16);
if (end <= p) { */
/* convert failed */
/* break;
} else {
addr[idx++] = val;
p = end;
if (*p == ':'|| *p == '-') {
p++;
} else {
break;
}
}
}
if (idx == 6) {
printk("Setup ethernet address to %pM\n", addr);
memcpy(dm9000_setup.param_addr, addr, 6);
}
return 1;
} */
EXPORT_SYMBOL(s3c_device_dm9000);
//__setup("ethmac=", dm9000_set_mac);
//#endif
/*static struct map_desc mini6410_iodesc[] = {
{ */
/* LCD support */
/* .virtual = (unsigned long)S3C_VA_LCD,
.pfn = __phys_to_pfn(S3C_PA_FB),
.length = SZ_16K,
.type = MT_DEVICE,
},
#ifdef CONFIG_DM9000
{
.virtual = (u32)S3C64XX_VA_DM9000,
.pfn = __phys_to_pfn(S3C64XX_PA_DM9000),
.length = S3C64XX_SZ_DM9000,
.type = MT_DEVICE,
},
#endif
}; */
static struct platform_device *smdk6410_devices[] __initdata = {
#ifdef CONFIG_SMDK6410_SD_CH0
&s3c_device_hsmmc0,
#endif
#ifdef CONFIG_SMDK6410_SD_CH1
&s3c_device_hsmmc1,
#endif
&s3c_device_i2c0,
&s3c_device_i2c1,
&s3c_device_fb,
&s3c_device_usb,
&s3c_device_usb_hsotg,
&smdk6410_lcd_powerdev,
//#ifdef CONFIG_DM9000
&s3c_device_dm9000,
//#endif
&smdk6410_smsc911x,
};
static void __init smdk6410_machine_init(void)
{
s3c_i2c0_set_platdata(NULL);
s3c_i2c1_set_platdata(NULL);
s3c_fb_set_platdata(&smdk6410_lcd_pdata);
gpio_request(S3C64XX_GPN(5), "LCD power");
gpio_request(S3C64XX_GPF(13), "LCD power");
gpio_request(S3C64XX_GPF(15), "LCD power");
i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
}
MACHINE_START(SMDK6410, "SMDK6410")
/* Maintainer: Ben Dooks <ben@fluff.org> */
.phys_io = S3C_PA_UART & 0xfff00000,
.io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C64XX_PA_SDRAM + 0x100,
.init_irq = s3c6410_init_irq,
.map_io = smdk6410_map_io,
.init_machine = smdk6410_machine_init,
.timer = &s3c24xx_timer,
MACHINE_END
Juergen Beisert
a) First learn how to show your work on existing file as a diff file. Nobody is interested in your full quotes. b) why you are using the SMDK6410 platform? I thought you are working on a Tiny6410 platform????
Bagrat
Hi All I have programmed DM9000A chip by FPGA. My operation mode is 16 bit. I programmed any register in DM9000A (Ethernet Controller with General Processor Interface) without F4, F5, FA and FB address registers. When I set register address (F4 or F5 or FA or FB) then set data value (Memory Data Raed/Write address Register Low/High Byte) the hardware didn't answer or receive (Memory Data Raed/Write address Register Low/High Byte) data value. What can be the problem? For example in steps: Step 1. I write F4 register address (0xF4), Step 2. I write Data Value (Memory Data Read Address Register Low Byte) (0x08), Step 3. I write F1 register address (0xF1) (Memory Data Read Command Without Address Increment Register), Step 4. I read data from buffer memory, I see data value but data value isn't in register address low byte location from (0x08), Step 5. After that I write F4 register address (0xF4), Step 6. Then I read F4 register value the chip return (0x00). Will you send me or show example with read/write buffer memory commands and timing diagram using Memory Data Read/Write Address Register Low/High Byte (F4, F5, FA and FB) registers? With Best Regards Bagrat Karyan